When using Intel MAX® 10 ADC, there are restrictions on GPIO placement, but a Critical Warning is reported for pins placed in an I/O bank outside the restrictions. How should I handle this?

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Intel: When using the MAX® 10 ADC, there are restrictions on GPIO placement, but a Critical Warning is reported even for pins placed in I/O Banks outside the restrictions. What should I do?

MAX IP

Category: Specifications
Tools: Quartus® Prime
Device: MAX®10

Contains I/O Bank information restricted to documentation.

Intel® MAX® 10 General Purpose I/O User Guide
https://www.altera.com/en_US/pdfs/literature/hb/max-10/ug_m10_gpio.pdf
(Search for Geometry-Based I/O Restrictions Related to ADC Usage.)

If message ID:16248 occurs in other I/O Banks, you can ignore it.

Knowledge database
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd03032016_970.html

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