Intel: When using a SoC device and implementing Nios® II on the FPGA side, is it possible to use the SDRAM controller on the Hard Processor System (HPS) side as work memory for Nios® II?

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Intel: In the case of implementing Nios® II on the FPGA side when using an SoC device, is it possible to use the SDRAM controller on the Hard Processor System (HPS) side as Nios® II work memory?

SoC FPGA Nios II

Category: Nios® II, SoCs
Tools: Quartus® Prime
Device: Cyclone® V

Connect to FPGA2HPS or FPGA2SDRAM port via Address_Span_Extender IP.
Please also check the contents of the Knowledge Data Base below.

Why doesn't my NIOS II recognize the HPS interface as a memory when it attached via Address Span Extender?
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07242014_134.html

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