Intel: After successfully simulating in Simulink with a design using the DSP Builder Standard Blockset, when trying to convert the design to HDL using Signal Compiler, the following occurs at the Analyze DSP Builder System stage: An error has been reported. Please tell me what to do.

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Intel: After successfully simulating in Simulink with a design using the DSP Builder standard blockset, when I tried to convert the design to HDL using Signal Compiler, during the Analyze DSP Builder System stage I got the following: error was reported. Please tell me what to do.

DSP/Filter

Category: DSP
Tool: DSP Builder
device:-

This may be caused by Japanese characters in the path name of the project folder where the mdl file is located.

<Message>

Info: Analyzing Simulink model
Info: Analysis was successful
Info: Generating HDL
Info: Creating Quartus Prime Project <path name with double-byte characters>
(Omitted)
Info: ********************************************
Info: Running Quartus Prime Shell
(Omitted)
Info: Command: quartus_sh t <path name with half-width alphanumeric characters>\generateProject1896819074759753234.tcl
-----------------------------------------------
missing close-bracket
while executing
"set projectdir "<path name with double-byte characters>"
(file "C:\Users\elsfae\AppData\Local\Temp\generateProject17199759454078390.tcl" line 2)
------------------------------------------------
Error: Failed to create Quartus Prime project topquantize in directory <path name with double-byte characters>.
Error: Error during compilation: Failed to create Quartus Prime project settings

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