Intel: How are the unused pins of the Hard Processor System (HPS) configured in the Arria® 10 SoC?
Category: Specifications
Tools: Quartus® Prime
Device: Arria® 10
Depends on the Unused Pins setting in Quartus® Prime.
Compile in Quartus® Prime with unused pins and check the compilation report.
(Check Compilation Report ⇒ Fitter ⇒ Resource Section ⇒ All Package Pins.)
For unused pin settings, please refer to the following document.
・[Quartus® Getting Started Guide - How to set device options]
https://www.macnica.co.jp/business/semiconductor/articles/intel/95569/
See here for the handling of unused pins in Arria® 10 SoC.
・[Intel® Arria® 10 GX, GT, and SX Device Family Pin Connection Guidelines]
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-10/pcg-01017.pdf
(See HPS Peripheral Pins.)
Most of the pins are written as below and set the input with a weak pull-up.
If unused, program it in the Quartus Prime software as an input with a weak pull-up.
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