Intel: Is it possible that a request accessed in the order of write → read on the SDRAM port (F2H) of the Hard Processor System (HPS) is overtaken inside the HPS or on the AXI bus and the order is changed?

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Intel: Is it possible that a request accessed in the order of write → read on the SDRAM port (F2H) of the Hard Processor System (HPS) will be overtaken inside the HPS or on the AXI bus and the order will be changed?

SoC FPGAs

Category: SoCs
tool:-
Device: Cyclone® V

The order of access may not be guaranteed depending on the configuration and settings.

The ARM processor defines three types of memory, and the memory type is set in the MMU.
See ARM documentation for details on each memory type. (Registration to ARM's site is required.)

Cortex-A Series Programmers Guide 9.1 ARM Memory Order Model
https://silver.arm.com/download/Software/BX100-DA-98002-r0p0-00rel0/DEN0013_cortexA_J_stamp.pdf

Also, although it is an external site, there is also content that explains it in an easy-to-understand manner, so please take a look at it as well.
https://www.aps-web.jp/academy/ca/10/

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