Category: Simulation
Tools: ModelSim®
device:-


In the case of Verilog-HDL, the signal to be pulled down is declared as a pulldown with the same signal name separately from the wire declaration.

example)
wire data; // target signal for pull-down

pulldown (data); //Describe the pull-down on the board ←Specific description example

Note that this description can only be used on the test bench (simulation).