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Intel: There is a path from the input pin to the first stage FF that is not reported in the Timing Report.
Quartus Prime
Timing constraints/analysis
Category: Timing Constraint/Analysis
Tools: Quartus® Prime
device:-
It is not reported in the Timing Report when it is set to Virtual Pin and the target path is involved.
Therefore, if the corresponding input pin is set to Virtual Pin, it must be set to OFF.
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