Category: Timing Constraint/Analysis
Tools: Quartus® Prime
Device: ー


Both MDC and MDIO are synchronous to the clock input from the TSE MAC clk port.
Since MDIO is output 2 clocks after MDC is output, for example, if CLK=100MHz and MDC is 2.5MHz (period=400ns), tsu=about 380ns and th=about 20ns when latched on the other side. increase.

The MDC/MDIO specification is ±10ns, so there is a considerable amount of margin without applying SDC, but with SDC you can issue a timing report.
Even if the result of timing analysis is fail, analyze with SDC like the example below using clk as the analysis clock. You can use slack for calculations.

set_output_delay -clock [ get_clocks clk ] 2 [ get_ports {mdc} ]
set_input_delay -clock [ get_clocks clk ] 2 [ get_ports {mdio} ]
set_output_delay -clock [ get_clocks clk ] 2 [ get_ports {mdio} ]