Intel: Please tell me about the arbiter priority processing of the Cyclne® V SoC's SDRAM Controller.

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Intel: Please tell us about the arbiter priority processing of the Cyclne® V SoC's SDRAM Controller.

SoCFPGA IP

Category: SoCs
tool:-
Device: Cyclone® V

The SDRAM Controller arbitration has the concept of Priority and Weight.

Priority sets which can be accessed preferentially during simultaneous access.
Weight sets which can be accessed preferentially among accesses with the same Priority. By default, MPU and L3 master are set to Highest Priority.

You can change the settings in the mppriority and mpweight registers respectively.

Reference information
Cyclone V Hard Processor System Technical Reference Manual
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cv_5v4.pdf
(Search for Example Using MPFE Priority and Weights.)

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