Intel: Are there any known issues with simulating PLL IP using Verilog HDL on Cyclone® 10 LP?

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Intel: Are there any known issues with simulating PLL IP with Verilog HDL in Cyclone® 10 LP?

IP clock/PLL

Category: Simulation
Tools: Quartus® Prime, ModelSim
Device: Cyclone® 10

When running RTL level simulation with Verilog HDL in Quartus® Prime Standard Edition or Lite Edition v17.0 and v17.1, Cyclone® 10 LP ALTPLL simulation model is not instantiated.
Therefore, the output clock of the PLL cannot be simulated correctly.

This issue does not apply when running simulations using VHDL.
It will be fixed in a future released version of Quartus® Prime.

Until this is fixed, please simulate the ALTPLL IP in VHDL with Cyclone® 10 LP as the target device.

Reference information
Is there a known issue with simulating the Cyclone 10 LP PLL IP using Verilog?
https://www.altera.com/support/support-resources/knowledge-base/component/2017/why-are-there-no-outputs-when-simulating-the-cyclone-10-lp-pll-i. html

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