What kind of circuit is the Adapter Logic required when connecting a PHY that does not support Gigabit Etnernet to Intel: Ethernet MAC (EMAC) using MII?

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Intel: What kind of circuit is the Adapter Logic required when connecting a PHY that does not support Gigabit Ethernet to an Ethernet MAC (EMAC) via MII?

Category: SoCs
tool:-
Device: Cyclone® V

Hard Processor System (HPS) Since the hard block to the FPGA Fabric side is output by the port standardized by the GMII protocol, the signal is converted to the MII protocol within the FPGA Fabric and connected to the I/O on the FPGA side. will be

Reference information
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cv_5v4.pdf
(Search for EMAC to FPGA Routing Example and FPGA EMAC I/O Signals.)

https://www.altera.com/en_US/pdfs/literature/an/an706.pdf

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