Intel: I am implementing Cyclone® V's PLL Dynamic Phase Shift based on AN-661, but the amount of shift I set is not achieved.

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Intel: Cyclone® V's PLL Dynamic Phase Shift is implemented with reference to AN-661, but the shift amount is not set.

Clock/PLL

Category: Quartus® Prime
Tools: Quartus® Prime
Device: Cyclone® V

Reset must be entered in the order of PLL Reconfig IP → PLL.
Note that common reset does not work properly.

Reference information
https://www.altera.com/en_US/pdfs/literature/an/an661.pdf

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