Category: Specifications
tool:-
Device: Cyclone® 10


The MSEL[*] pins are pins that determine the configuration mode of the FPGA.
The Cyclone® 10 GX MSEL pin handling should be as follows:

• High: Connect directly to VCCPGM (can also be through a 0Ω resistor)
• Low: Connect directly to GND (can also be through a 0Ω resistor)

Be sure to check the latest English version of the document when designing.

Reference information
https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/cyclone-10/pcg-01022.pdf (English version)
https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/dp/cyclone-10/pcg-01022-j.pdf (Japanese version)
(See MSEL pin description.)

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
(Search for MSEL Pin Settings.)