Category: External memory interface
Tools: Quartus® Prime
Device: Arria® 10


Connect the master signal to the master and the slave signal to the slave.

For reference, in the Example Design, emif_usr_clk from the master's memory IP is connected to emif_usr_clk in the master's user circuit, and emif_usr_reset_n from the slave's memory IP is connected to emif_usr_reset_n in the slave's user circuit.

If there is no circuit to reset the master and slave individually, the master signal can be shared with the slave.