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Intel: What are the conditions for clearing (negating) the IRQ for the 16550 UART IP?
IP
Category: IP
Tools: Quartus® Prime
device:-
Since ier_dlh is the interrupt enable register, setting the 1st bit (etbei_dlh1) to 0 can lower the interrupt during transmission.
When set to 1, the interrupt enable is unmasked and the IRQ returns to its original state.
In addition, it is possible to mask the IRQ during reception with the 0th bit of ier_dlh (erbfi_dlh0).
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