Category: SoCs
Tools: Quartus® Prime
Device: Cyclone® V


Is possible.
There is a component called FPGA Manager on the HPS side, and you can reset the FPGA from HPS by manipulating nconfigpull of this ctrl register.

Reference information
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cv_5v4.pdf
(Please refer to the item of Reset Phase)

When resetting the FPGA side, the 0th bit en bit must also be enabled.
(Please refer to the ctrl register map in the above document.)

HPS itself can also be reset by Swcoldrstreq and Swwarmrstreq in the Reset Manager's ctrl register.
(Search for Swcoldrstreq or Swwarmrstreq in the above materials.)