Category: SoCs
Tools: Quartus® Prime
Device: Cyclone® V


It is possible to reset only from the FPGA side to the HPS side.
A signal that resets the HPS side from the FPGA side can be set on Qsys.

It is possible to reset the HPS side from the FPGA side with the following three signals in the FPGA Interface tab ⇒ Resets item on the Hard Processor System parameter setting screen.
This reset does not reset the FPGA side.

• Enable FPGA-to-HPS debug reset request
• Enable FPGA-to-HPS warm reset request
• Enable FPGA-to-HPS cold reset request