Intel: Please tell me the supported bit numbers of Hard Processor System (HPS) SPI Master Core and Qsys SPI Core. Is there anything that supports 64bit?

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Intel: Please tell me the supported bitness of the Hard Processor System (HPS) SPI Master Core and Qsys' SPI Core. Do you have 64bit support?

SoC FPGAs

Category: Qsys
Tools: Quartus® Prime / Quartus® II
Device: Arria® V

HPS SPI Master is 16bit, Qsys SPI Core is 32bit.

Currently, 64bit compatible versions are not provided.
However, both SPI Master Cores may be able to handle this by manipulating the SSO signal.
For example, in Qsys' SPI Core, the receiving circuitry must be able to tolerate ss_n being asserted when a 32bit is sent twice.
Check the specifications of the opposing SPI Slave.

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