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Intel: When using MAX® 10 ADC, can adc_pll_clock and clock_clk have the same input frequency of 10MHz?
MAX
Clock/PLL
IP
Category: Specifications
Tools: Quartus® Prime
Device: MAX®10
Although it is not documented, it is not possible to operate with the same input frequency for adc_pll_clock and clock_clk.
Connect clock_clk to a clock with a frequency of at least 25MHz.
It will be clarified in future revisions of the document.
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