Intel: I use Clock Source in Qsys to distribute clock and reset signals to each module. The synchronization circuit automatically enters the reset signal input from the outside, but is there a way to distribute it to each module without synchronizing it?

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Intel: I use Clock Source in Qsys to distribute clock and reset signals to each module. A reset signal that is input from the outside automatically enters a synchronization circuit. Is there a way to distribute it to each module without synchronizing it?

Platform Designer Clock/PLL

Category: Quartus® Prime / Quartus® II (Qsys)
Tools: Quartus® Prime / Quartus® II
device:-

Qsys does not allow asynchronous resets.
It is a specification that the reset synchronization circuit automatically enters.

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