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Is it better to put a pull-up or pull-down resistor in the Stratix® 10 MSEL pin handling?
Category: Specifications
tool:-
Device: Stratix® 10
The MSEL[*] pins are pins that determine the configuration mode of the FPGA.
Treat the Stratix® 10 MSEL pins as follows:
・High: Connect to VCCIO_SDM via 4.7KΩ
・Low: Connected to GND via 4.7KΩ
Be sure to check the latest English version of the document when designing.
Reference information
https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/stratix-10/pcg-01020.pdf
(See MSEL pin description.)
https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/stratix-10/ug-s10-config.pdf
(Search for MSEL Settings.)
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