Category: Specifications
tool:-
Device: Arria® 10


The MSEL[*] pins are pins that determine the configuration mode of the FPGA.
Arria® 10 MSEL pin handling should be as follows:

・High: Directly connected to VCCPGM (can also be connected via a 0Ω resistor)
・Low: Connect directly to GND (possible through a 0Ω resistor)

Be sure to check the latest English version of the document when designing.

Reference information
https://www.intel.co.jp/content/dam/altera-www/global/en_US/pdfs/literature/dp/cyclone-v/pcg-01014.pdf
(See MSEL pin description.)

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_5v2.pdf
(Search for MSEL Pin Settings.)