Category: Specifications
tool:-
Device: Arria® V


The MSEL[*] pins are pins that determine the configuration mode of the FPGA.
Arria® V MSEL pin handling should be as follows:

• High: Connect directly to VCCPGM (can also be through a 0Ω resistor)
• Low: Connect directly to GND (can also be through a 0Ω resistor)

Be sure to check the latest English version of the document when designing.

Reference information
https://www.intel.co.jp/content/dam/altera-www/global/en_US/pdfs/literature/dp/arria-v/pcg-01013.pdf (Arria® V GT/GX/ST/SX )
https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/dp/arria-v/pcg-01016.pdf (Arria® GZ)
(See MSEL pin description.)

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-v/av_5v2.pdf
(Search for MSEL Pin Settings.)