Category: DSP
Tools: Quartus® Prime / Quartus® II, DSP Builder
device:-


If you create an FPGA hardware model with the Advanced Blockset, the input and output pins will be Virtual Pins by default on Quartus® Prime / Quartus® II.
Therefore, disable the Virtual Pin setting in Quartus® Prime / Quartus® II Assignmnet Editor or .qsf file, and set the pin assignment and I/O standard according to the board with Pin Planner or .qsf. .

To use the Hardware in the Loop (HIL) feature, you can avoid the Virtual Pin setting by setting DSPBA_Features.VirtualPins = false.

Reference information
https://www.altera.com/en_US/pdfs/literature/hb/dspb/hb_dspb_adv.pdf
(Search for HIL in Advanced Blockset.)