Category: SoCs
tool:-
Device: Cyclone® V


SCU Parity does not have Error Injection feature.

All 16 bits defined in the following register (sysmgr.parityinj) support the parity injection function of Cyclone® V SoC.
https://www.altera.com/hps/en_us/cyclone-v/hps.html#topic/sfo1410067847075.html

A list of parity error signals is provided in "A.10. Parity error signals" in the Cortex-A9 MPCore Technical Reference Manual.
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407g/Cjaceghh.html

PARITYFAILn[7:0] and PARITYFAILSCU[N:0] are posted as error signals, but the bits corresponding to PARITYFAILn[7:0] are 16 bits of sysmgr.parityinj (8 bits x 2 CPUs = 16 bits) corresponds to
On the other hand, there is no register/bit for injection corresponding to SCU parity error PARITYFAILSCU[N:0].