Is it possible to have a fixed burst length when accessing the FPGA fabric from a Hard Processor System (HPS)?

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Is it possible to have a fixed burst length when accessing the FPGA fabric from the Hard Processor System (HPS)?

SoC FPGAs

Category: SoCs
Tools: Quartus® Prime / Quartus® II
Device: Cyclone® V

By using the Avalon-MM Pipeline Bridge, it is possible to set the maximum burst length.

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