Can the clock used for PLL sharing in the DDR controller IP be used in the user circuit?

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Can the clock used by the DDR controller IP for PLL sharing be used by the user circuit?

IP Clock/PLL

Category: External memory interface
Tools: Quartus® Prime
Device: Cyclone® V

It is not recommended to connect the clock used for PLL sharing to the user circuit as the clock delay will change depending on the controller IP settings.

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