What is the maximum burst length that can be accessed when burst accessing user logic from the Cyclone® V SoC FPGA's Hard Processor System (HPS)?

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When bursting access to user logic from the Cyclone® V SoC FPGA's Hard Processor System (HPS), what is the maximum burst length that can be accessed?

SoC FPGAs

Category: SoCs
tool:-
Device: Cyclone® V

The I/F of HPS is AXI3.
The maximum burst length (AxLEN) from the HPS to the user logic is 16 because the AXI3 specification has a maximum burst length (AxLEN) of 16.

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