On Stratix® V, interrupt notifications to PCI-Express (PCIe) using V-Series Avalon-MM DMA for PCI Express cannot be detected on the PC side. Please tell me how a user can issue an MSI at any time when using this IP.

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Interrupt notification to PCI-Express (PCIe) using V-Series Avalon-MM DMA for PCI Express on Stratix® V cannot be detected on the PC side. Please let me know how the user can issue MSI at any time when using this IP.

PCI Express

Category: PCI-Express (PCIe)
Tools: Quartus® Prime / Quartus® II
Device: Stratix® V

MSI is equivalent to issuing a Memory Write TLP (Mwr) to a specific address specified by the Host.
Therefore, an interrupt can be generated by accessing Txs of the IP and issuing Mwr.

The first method is to enable Export MSI/MSI-X conduit interfaces for IP.
When enabled, the IP outputs MsiIntfc_o[81:0].
Each bit allocation is as follows.

MsiIntf_o81 : Master enable
MsiIntf_o[80 }: MSI enable
MsiIntf_o[79:64] : MSI data
MsiIntf_o[63:0] : MSI address

Get the above address/data and use that value to access from Txs.
This notifies the host of the interrupt.

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