In the Streamline Performance Analyzer for the ARM® DS-5™ Intel® SoC FPGA Edition, captured data is sent via Ethernet from the target to the host PC running the DS-5™. /100Mbps/10Mbps) Are there any functional limitations at low transfer rates?

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In the Streamline Performance Analyzer for ARM® DS-5™ Intel® SoC FPGA Edition, captured data is sent from the target to the host PC running DS-5™ via Ethernet, but the Ethernet transfer rate (1000Mbps /100Mbps/10Mbps), will there be any functional limitations at low transfer rates?

SoC EDS/DS-5 SoC FPGA

Category: SoCs
Tool: SoC EDS
device:-

Assuming that the communication speed is slow or the load on the target is high, the following settings are possible.

The sample rate can be selected between 1KHz (default) and 100Hz (low).
Equipped with measurement buffer, 16Mbyte/8Mbyte/1Mbyte can be selected.

Reference information
http://infocenter.arm.com/help/topic/com.arm.doc.dui0482sj/DUI0482SJ_streamline_user_guide.pdf
(Search by sample rate or buffer mode.)

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