Where is the High Speed I/O and Low Speed I/O in the MAX® 10 FPGA?

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What is the location of High Speed I/O and Low Speed I/O in MAX® 10 FPGA?

MAX

Category: Specifications
Tools: Quartus® Prime / Quartus® II
Device: MAX®10

The I/O Banks Location is determined in advance for each device scale.

See the handbook and pinout files for details.

Reference information
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf
(Search for MAX 10 I/O Banks Locations.)

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html#MAX-10

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