When using the EPCS Flash Controller with Cyclone® III and Cyclone® IV, the generated Qsys system has ports dclk, sce, sdo, and data0. How should I connect them?

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When using the EPCS Flash Controller on Cyclone® III and Cyclone® IV, the generated Qsys system has dclk, sce, sdo, and data0 ports. How should I connect?

Platform designer IP

Category: Quartus® Prime / Quartus® II (Qsys)
Tools: Quartus® Prime / Quartus® II
Devices: Cyclone® III/Cyclone® IV, EPCQ/EPCS

Assign them in the top design as follows.

data0 ⇒ DATA0
sdo ⇒ DATA1, ASDO
dclk ⇒ DCLK
sce ⇒ FLASH_nCE

Also, when using the EPCS Flash Controller from a user program, it is necessary to set the Dual Purpose Pin so that it can be used as User I/O when the FPGA enters user mode.

Reference information
https://www.altera.com/en_US/pdfs/literature/ug/ug_embedded_ip.pdf
(See the Functional Description of the EPCS Serial Flash Controller Core.)

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