Regarding the frequency of ddr_dqs_base_clk output from the SDRAM PLL of Arria® V SoC, the documentation states that it varies depending on the speed grade. Could you please tell me the specific number?

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The document states that the frequency of ddr_dqs_base_clk output from the SDRAM PLL of Arria® V SoC varies depending on the speed grade.

SoC FPGA clock/PLL

Category: SoCs
tool:-
Device: Arria® V

ddr_dqs_base_clk is the same frequency as the operating frequency.
You can check the SDRAM PLL output frequency by entering the reference clock, preloader, and SDRAM PLL settings from the RocketBoards.org web page below.

http://rocketboards.org/foswiki/view/Documentation/PreloaderClockingCustomization131
(See Preloader Parameters and Compute Clocks.)

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