The BOOTSEL0 pin of the Cyclone® V SoC FPGA is shared with the UART1 RTS pin when two UART controllers are used. Can it be used as a UART pin after U-Boot is finished?

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The Cyclone® V SoC FPGA BOOTSEL0 pin is shared with the UART1 RTS pin when using two UART controllers. Can I use it as a UART pin after U-Boot finishes?

SoC FPGAs

Category: SoCs
tool:-
Device: Cyclone® V

A pull-up/down resistor for BOOTSEL is allowed as it can be shared without interfering with the slow interface signals.
Also, BOOTSEL1 and 2 pins are handled in the same way.

Reference information
https://www.altera.com/en_US/pdfs/literature/dp/cyclone-v/pcg-01014.pdf
(Search for BOOTSEL0.)

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