I would like to implement the I2C interface of the Hard Processor System (HPS) in Cyclone® V SoC FPGA using the FPGA pins, but how should I process it on the FPGA side to make SDA/SCL bidirectional?

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I would like to implement the I2C interface of the Hard Processor System (HPS) on the Cyclone® V SoC FPGA using pins on the FPGA side. is it?

SoC FPGAs

Category: SoCs
Tools: Quartus® Prime / Quartus® II
Device: Cyclone® V

In order to build an FPGA IO Interface with SDA / SCL bi-directional, it is necessary to prepare a buffer that configures Tristate IO on the port that can be seen as Conduit from Qsys on the design.
On the upper RTL, call and connect the ALT_IOBUF primitive.

Reference information
https://www.altera.com/en_US/pdfs/literature/an/an706.pdf
(Search for alt_iobuff.)

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