Is there a sequence regarding the timing relationship between mgmt_rst_reset and PCI Express* (PCIe*) core pin reset (nor)? Is it okay to cancel the reset for each one individually?

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Is there a sequence for timing relationship between mgmt_rst_reset and PCI Express* (PCIe*) core pin reset (nor)? Is there any problem in canceling the reset individually?

PCI Express

Category: PCIe*
tool:-
Device: Cyclone® V

mgmt_rst_reset is the reset signal for the Reconfiguration Controller IP.

Reference information
https://www.altera.com/en_US/pdfs/literature/ug/xcvr_user_guide.pdf
(Search for mgmt_rst_reset.)

This IP is a required module when using Transceiver IP such as PCIe*.
For specific connection, input the signal of the same source as pin_perst.
The order of reset release is Reconfiguration Controller ⇒ PCIe IP, but this operation is realized by the internal reset controller (altpcie_rs_serdes.v).

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