Category: PCI-Express (PCIe)
Tools: Quartus® Prime / Quartus II (Qsys)
Device: Arria® V


It is possible by using PIO with the following configuration.

■ PIO settings

• Width: 1
• Direction: Input
• Synchronously capture : Check
• Edge Type: FALLING
• Enable bit-clearing for edge capture register : Check
• Generate IRQ: Check
• IRQ Type : EDGE

■ How to connect PIO

• Connect PIO irq to PCIe RxmIrq
• Connect FRAME signal to in_port

⇒ Depending on the above PIO setting, an IRQ is issued at the falling edge.
⇒Hold IRQ until edge capture register is cleared

• Connect some Master such as Rxm_BAR to PIO Slave

With the above configuration, which can clear the IRQ by writing 1 to the edge capture register (offset: 0x3), it is possible to detect the falling edge of the FRAME signal with PIO and send an interrupt to RxmIrq of PCIe.
In addition, it is possible to hold interrupts by the edge capture register of PIO until they are cleared from the HOST side.

When the HOST confirms the interrupt contents and clears the PCIe (CRA) Status Register, please be careful to clear the PIO first.
If the PIO is cleared later, the interrupt will come in again immediately after clearing the PCIe (CRA) Status Register.

For how to use PIO, please refer to the following document.
https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu_nii51007.pdf
(Please refer to the item of PIO Core.)