When using Transceiver Native PHY under the conditions of Data rate (TX, RX): 1Gbps, Reference clock frequency (TX): 100MHz, Selected CDR reference clock frequency (RX): 100MHz, what kind of clock should be applied to each input pin? Should I connect?

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Data rate (TX, RX): 1Gbps, Reference clock frequency (TX): 100MHz, Selected CDR reference clock frequency (RX): 100MHz When using Transceiver Native PHY, what kind of clock should be applied to each input pin? Should I connect?

Category: Transceiver
Tools: Quartus® Prime / Quartus II
Device: Cyclone® V

The clocks to be connected to the following input pins are described.

tx_pll_refclk: 100 MHz sourced externally via refclk pin of transceiver bank
rx_cdr_refclk: common with tx_pll_refclk
tx_std_coreclkin (*1): Connect tx_std_clkout
rx_std_coreclkin (*1): Connect rx_std_clkout

Note that tx_parallel_data uses tx_std_clkout and rx_parallel_data uses rx_std_clkout to drive.

Also, for details on tx_std_coreclkin and rx_std_coreclkin, refer to the following documents.
https://www.altera.com/en_US/pdfs/literature/ug/xcvr_user_guide.pdf
(See the Cyclone V Transceiver Native PHY IP Core Overview Chapter.)

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