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Regarding the Ethernet Media Access Controller (EMAC) interface on the Hard Processor System (HPS) side of the Cyclone V SoC device, case 1: when using I/O on the HPS side, case 2: using I/O on the FPGA side What kind of interface do you support at each time?
Category: SoCs
Tools: Quartus® Prime / Quartus II
Device: Cyclone® V
When using I/O on the HPS side, only RGMII is available.
It can be GMII or MII when using FPGA side I/O and not using an adapter inside the FPGA circuit.
RMII, RGMII, and SGMII can be supported by using the I/O on the FPGA side and using an adapter within the FPGA circuit.
From v14.1 onwards, Qsys provides GMII to RGMII and GMII to SGMII conversion adapters.
When using RMII with versions prior to v14.1, you need to make your own adapter.
For details, please refer to the following documents.
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cv_5v4.pdf
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