When I want to connect Base Address Register 0 (BAR0) of PCI-Express (PCIe) to my Control Register Access (CRA) with Avalon-MM, I want to set the address of BAR0 to 0x0000_3000, but if I set the Base address to 0x0000_3000 , I got an error message "Only 0x0000_0000 or 0x0000_40000 is allowed" when generating the PCI Express (PCIe) Compiler with Qsys. In this case, are there rules for setting addresses?

Category: PCI-Express (PCIe)
tool:-
device:-


PCIe addressing has certain rules (limitations).
In this case, CRA has an address range of 0x0000 - 0x3fff, and it is necessary to set an address with that range as the boundary.

ex) 0x0, 0x4000, 0x8000, etc..