Category: Quartus® Prime / Quartus II (Platform Designer)
Tool: Quartus Prime / Quartus II
device:-


There is a component called Clock Crossing Bridge that can separate the master / slave clocks, and by inserting it between the components of different operating clocks, FIFO is inserted and pipelined, which is effective in designs with complicated clock configurations It will be the method.

However, this does not mean that you must use the Clock Crossing Bridge.
Platform Designer (Qsys) automatically inserts a Clock Crossing Adapter to accommodate clock domain differences.
The Clock Crossing Adapter adjusts through a handshake protocol or FIFO, so this can be an effective approach if you need to consider simple design configurations or latency.

Please refer to the following document for details.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer.pdf
(Please search with keywords such as clock crossing.)