If automate slave default insertion is enabled in Qsys, what is the behavior when accessing an undefined address? Also, what will happen if an undefined address is accessed from HPS (AXI Interface)?

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With Qsys automate slave default insertion enabled, what is the behavior when accessing an undefined address? What is the behavior when accessing an undefined address from HPS (AXI Interface)?

Platform Designer SoC FPGA

Category: Quartus® Prime / Quartus II (Qsys)
Tool: Quartus Prime / Quartus II
Device: Cyclone® V

A block called Default Slave is inserted in the Qsys Interconnect, and accesses that Default Slave when accessing an undefined address.

DECEER is returned in bresp for Write access to an undefined address from HPS (AXI Interface), and in rresp for Read access.

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