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I have set the Autonomous PCIe HIP mode to comply with the PCI-Express (PCIe) link-up time regulation, but why is it possible to set the Enable CvP_CONFDONE pin even when the CvP mode is not used?
PCI Express
Category: Quartus® Prime
Tools: Quartus Prime
Device: Arria® V
If the Configuration via Protocol setting is Off, setting the Enable CvP_CONFDONE pin has no effect.
It will be improved in Quartus Prime v17.0.
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