Category: External memory interface
Tools: Quartus® Prime / Quartus II
Device: Arria® 10


For 64-bit width, it uses 3 banks, so it uses 3 I/O PLLs.
The PHY Clock Tree architecture can be expected to suppress jitter and duty cycle distortion and maximize the data valid window.

For details, refer to the document below.
https://www.altera.com/en_US/pdfs/literature/hb/external-memory/emi_ip.pdf
(Search for PLL Reference Clock Networks.)

https://www.altera.com/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
(Search for Required I/O Banks for Interface Widths.)