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How many bits of data can the LDVS SERDES block in Arria 10 devices support?
Arria
Category: Specifications
tool:-
Device: Arria® 10
The maximum data width from the LVDS SERDES block to the internal logic (FPGA Fabric) is 10 bits.
For more information, please refer to the following documents.
https://www.altera.com/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
(Search for Receiver Block Diagram.)
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