In the Hard Processor System (HPS) Peripheral Pins settings, the pin selections include HPS_I/O_Set_0, HPS_I/O_Set_1, and FPGA. What do these mean?

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In the Hard Processor System (HPS) Peripheral Pins settings, the pins are HPS_I/O_Set_0, HPS_I/O_Set_1, and FPGA. What does this mean?

SoC FPGAs

Category: SoCs
Tools: Quartus® Prime / Quartus II
device:-

Each peripheral is pin multiplexed with at least one.
Therefore, it is possible for the user to select which pin to use from the list Box.

For more information on pins, please refer to the following documents:
https://www.altera.com/support/literature/lit-dp.html#Cyclone-V
https://www.altera.com/en_US/pdfs/literature/dp/cyclone-v/pcg-01014.pdf

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