Category: Simulation
Tools: ModelSim®-Altera®
Device: Arria® 10 / Stratix® V / Arria V / Cyclone® V


There is a problem with the simulation model (.vho file) created for functional simulation when using the PLL in VHDL.
An error occurs due to inconsistency with the library pre-compiled in ModelSim-AE.

It can be avoided by deleting the description that causes the error by the following method and compiling.

1. Open the altera_lnsim_component.vhd file.
   This file is for ModelSim-AE 10.4b
   <install directory>/modelsim_ae/altera/vhdl/src/altera_lnsim/altera_lnsim_components.vhd
   is in
2. In the file, delete (or comment out) the description of PLL_CTR_RESYNC : integer := 0 on line 271, and also delete the semicolon (;) at the end of the previous line.
   (It's easy to search for "CTR_RESYNC" etc.)
   
   (Correction example)
   clock_name_global_7 : string := "false";
   clock_name_global_8 : string := "false" --;
   --PLL_CTR_RESYNC : integer := 0
   );
   
   
3. Recompile altera_lnsim_component.vhd.
   
   (Command example)
   vcom -work altera_lnsim $QUARTUS_DIR/../modelsim_ae/altera/vhdl/src/altera_lnsim/altera_lnsim_components.vhd
   
   
4. Recompile the Altera PLL design file (.vho).
   Then run the load.

参考
https://www.altera.com/support/support-resources/knowledge-base/solutions/fb332640.html