<Unconstrained Paths/Clock Status Summary>
nios2_system_dual:u0|...|alt_dual_boot:alt_dual_boot|ru_clk

(The ... in the middle is omitted. Please refer to the file below for an example that describes everything.)

Category: Timing Constraint/Analysis
Tools: Quartus® Prime / Quartus II
Device: MAX®10


The MAX 10 FPGA Configuration User Guide states that the Altera Dual Configuration IP generates RU_CLK that runs at half the rate of the input clock.
Try adding the following to your SDC.

create_generated_clock -name ru_clk -source [get_pins { altera_dual_boot IP input clock source }] -divide_by 2 [get_registers *ru_clk]

ELS7132_example__1.txt

Full text