What clock frequencies can I input to the HPS_CLK1 pin of the Cyclone V SoC device?

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What clock frequencies can be input to the HPS_CLK1 pin of Cyclone V SoC devices?

SoC FPGA clock/PLL

Category: SoCs
Tools: Quartus® Prime / Quartus II
Device: Cyclone® V

The HPS_CLK1 pin in Cyclone V SoC devices should have a clock input in the range of 10-50 MHz.

For details, refer to the document below.
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cv_5v4.pdf
(Search with the keyword OSC1 Clock Group Clock.)

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