Intel: According to the Arria® 10 FPGA Handbook and the LVDS SERDES Intel FPGA IP User Guide, it seems that the LVDS Transmitter can output a center-aligned clock, but where can I set this?

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Intel: Looking at the Arria® 10 FPGA Handbook and the LVDS SERDES Intel FPGA IP User Guide, it seems that the LVDS Transmitter can output the clock center-aligned, where can I configure this?

Arria

Category: Specifications
Tools: Quartus® Prime / Quartus II
Device: Arria® 10

The relationship between the output clock and data of the LVDS SERDES Intel FPGA IP is set by the following items on the Transmitter Settings tab in the IP Parameter Editor.

Desired tx_outclock phase shift (degrees):
Tx_outclock division factor (degrees) :

<Example: Center alignment setting (When setting to Division Factor x8, Phase Shift 180°>

Desired tx_outclock phase shift: 180
Tx_outclock division factor: 8

<Example: Edge alignment setting (When setting to Division Factor x8, Phase Shift 0°>

Desired tx_outclock phase shift: 0
Tx_outclock division factor: 8

For details, refer to the document below.

https://www.intel.com/content/www/us/en/docs/programmable/683461/current/clocking-differential-transmitters.html
(See 5.6.6.1. Clocking Differential Transmitters)
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You can set the phase of the clock in relation to the data at 0° or 180° (edge- or center-aligned).
The I/O PLLs provide additional support for other phase shifts in 45° increments.

https://www.intel.com/content/www/us/en/docs/programmable/683520/22-1-20-0-1/setting-the-transmitter-output-clock.html
(See Figure 8. 180° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8)

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